Çѱ¹Á¤º¸Åë½ÅÇÐȸ ³í¹®Áö (Journal of the Korea Institute of Information and Communication Engineering)
ÇѱÛÁ¦¸ñ(Korean Title) |
ECB/CTR ¿î¿µ¸ðµå¸¦ Áö¿øÇÏ´Â 8.3 Gbps ÆÄÀÌÇÁ¶óÀÎ LEA ¾ÏÈ£/º¹È£ ÇÁ·Î¼¼¼ |
¿µ¹®Á¦¸ñ(English Title) |
8.3 Gbps pipelined LEA Crypto-Processor Supporting ECB/CTR Modes of operation |
ÀúÀÚ(Author) |
¼º¹ÌÁö
½Å°æ¿í
Mi-Ji Sung
Kyung-Wook Shin
|
¿ø¹®¼ö·Ïó(Citation) |
VOL 20 NO. 12 PP. 2333 ~ 2340 (2016. 12) |
Çѱ۳»¿ë (Korean Abstract) |
128/192/256-ºñÆ®ÀÇ 3°¡Áö ¸¶½ºÅÍÅ° ±æÀÌ¿Í ECB, CTR ¿î¿µ¸ðµå¸¦ Áö¿øÇÏ´Â LEA (Lightweight Encryption Algorithm) ¾ÏÈ£/º¹È£ ÇÁ·Î¼¼¼¸¦ ¼³°èÇÏ¿´´Ù. ¶ó¿îµå ºí·ÏÀ» 16´Ü ÆÄÀÌÇÁ¶óÀÎ ±¸Á¶¿Í 128 ºñÆ® µ¥ÀÌÅÍÆнº·Î ±¸ÇöÇÏ¿© °í¼Ó ¾ÏÈ£/º¹È£ 󸮰¡ ÀÌ·ç¾îÁöµµ·Ï ÇÏ¿´´Ù. ¸¶½ºÅÍÅ° ±æÀÌ¿¡ µû¶ó 12/14/16 ÆÄÀÌÇÁ¶óÀÎ ½ºÅ×ÀÌÁö¸¦ °ÅÃÄ ¾ÏÈ£/º¹È£È°¡ ÀÌ·ç¾îÁö¸ç, °¢ ÆÄÀÌÇÁ¶óÀÎ ½ºÅ×ÀÌÁö¿¡¼´Â ¶ó¿îµå º¯È¯ÀÌ 2ȸ ¹Ýº¹ ¼öÇàµÈ´Ù. ¼¼ °¡Áö ¸¶½ºÅÍÅ° ±æÀÌ¿¡ ´ëÇÑ ¾ÏÈ£/º¹È£ Å° ½ºÄÉÁÙ¸µÀÇ Çϵå¿þ¾î ÀÚ¿øÀÌ °øÀ¯µÇµµ·Ï ¼³°è¸¦ ÃÖÀûÈÇÏ¿´´Ù. Å° ½ºÄÉÁÙ·¯¿¡¼ »ý¼ºµÇ´Â ¶ó¿îµåÅ°´Â 32°³ÀÇ ¶ó¿îµåÅ° ·¹Áö½ºÅÍ¿¡ ÀúÀåµÇ¾î ¸¶½ºÅÍÅ°°¡ °»½ÅµÉ ¶§±îÁö ¹Ýº¹ÀûÀ¸·Î »ç¿ëµÈ´Ù. ¼³°èµÈ LEA ÇÁ·Î¼¼¼´Â FPGA ±¸ÇöÀ» ÅëÇØ Çϵå¿þ¾î µ¿ÀÛÀ» °ËÁõÇÏ¿´À¸¸ç, Xilinx ISE¸¦ ÀÌ¿ëÇÑ ÇÕ¼º °á°ú·Î ÃÖ´ë µ¿ÀÛ ÁÖÆļö 130 MHz¿¡¼ 8.3 GbpsÀÇ ¼º´ÉÀ» °®´Â °ÍÀ¸·Î Æò°¡µÇ¾ú´Ù.
|
¿µ¹®³»¿ë (English Abstract) |
A LEA (Lightweight Encryption Algorithm) crypto-processor was designed, which supports three master key lengths of 128/ 192/256-bit, ECB and CTR modes of operation. To achieve high throughput rate, the round transformation block was designed with 128 bits datapath and a pipelined structure of 16 stages. Encryption/decryption is carried out through 12/14/16 pipelined stages according to the master key length, and each pipelined stage performs round transformation twice. The key scheduler block was optimized to share hardware resources that are required for encryption, decryption, and three master key lengths. The round keys generated by key scheduler are stored in 32 round key registers, and are repeatedly used in round transformation until master key is updated. The pipelined LEA processor was verified by FPGA implementation, and the estimated performance is about 8.3 Gbps at the maximum clock frequency of 130 MHz.
|
Å°¿öµå(Keyword) |
LEA
ºí·Ï¾ÏÈ£
Á¤º¸º¸¾È
°í¼º´É ¾ÏÈ£
¿î¿µ¸ðµå
LEA
block cipher
information security
high performance encryption
modes of operation
|
ÆÄÀÏ÷ºÎ |
PDF ´Ù¿î·Îµå
|