Çѱ¹Á¤º¸Åë½ÅÇÐȸ ³í¹®Áö (Journal of the Korea Institute of Information and Communication Engineering)
ÇѱÛÁ¦¸ñ(Korean Title) |
233-ºñÆ® ÀÌÁøü Ÿ¿ø°î¼±À» Áö¿øÇÏ´Â ¾ÏÈ£ ÇÁ·Î¼¼¼ÀÇ Àú¸éÀû ±¸Çö |
¿µ¹®Á¦¸ñ(English Title) |
A small-area implementation of cryptographic processor for 233-bit elliptic curves over binary field |
ÀúÀÚ(Author) |
¹Úº´°ü
½Å°æ¿í
Byung-Gwan Park
Kyung-Wook Shin
|
¿ø¹®¼ö·Ïó(Citation) |
VOL 21 NO. 07 PP. 1267 ~ 1275 (2017. 07) |
Çѱ۳»¿ë (Korean Abstract) |
NIST Ç¥ÁØ¿¡ Á¤ÀÇµÈ ÀÌÁøü(binary field) »óÀÇ 233-ºñÆ® Ÿ¿ø°î¼±À» Áö¿øÇϴ Ÿ¿ø°î¼± ¾ÏÈ£(elliptic curve cryptography; ECC) ÇÁ·Î¼¼¼¸¦ ¼³°èÇÏ¿´´Ù. Ÿ¿ø°î¼± ¾ÏÈ£ ½Ã½ºÅÛÀÇ ÇÙ½É ¿¬»êÀÎ ½ºÄ®¶ó Á¡ °ö¼ÀÀ» ¼öÁ¤Çü Montgomery ladder ¾Ë°í¸®µëÀ» ÀÌ¿ëÇÏ¿© ±¸ÇöÇÔÀ¸·Î½á ´Ü¼ø Àü·ÂºÐ¼®¿¡ °ÀÎÇϵµ·Ï ÇÏ¿´´Ù. Á¡ µ¡¼À°ú Á¡ µÎ¹è ¿¬»êÀº ¾ÆÇÉ(affine) ÁÂÇ¥°è¸¦ ±â¹ÝÀ¸·Î À¯ÇÑü ɧɦ ÉåÉÖÉÖÉ×É× Éæ »óÀÇ °ö¼À, Á¦°ö, ³ª´°¼ÀÀ¸·Î ±¸ÇöÇÏ¿´À¸¸ç, shift-and-add ¹æ½ÄÀÇ °ö¼À±â¿Í È®Àå À¯Å¬¸®µå ¾Ë°í¸®µëÀ» ÀÌ¿ëÇÑ ³ª´°¼À±â¸¦ Àû¿ëÇÔÀ¸·Î½á Àú¸éÀûÀ¸·Î ±¸ÇöÇÏ¿´´Ù. ¼³°èµÈ ECC ÇÁ·Î¼¼¼¸¦ Virtex5 FPGA·Î ±¸ÇöÇÏ¿© Á¤»ó µ¿ÀÛÇÔÀ» È®ÀÎÇÏ¿´´Ù. 0.18§ °øÁ¤ÀÇ CMOS ¼¿ ¶óÀ̺귯¸®·Î ÇÕ¼ºÇÑ °á°ú 49,271 GE·Î ±¸ÇöµÇ¾ú°í, ÃÖ´ë 345 MHzÀÇ µ¿ÀÛ ÁÖÆļö¸¦ °®´Â´Ù. ½ºÄ®¶ó Á¡ °ö¼À¿¡ 490,699 Ŭ·Ï »çÀÌŬÀÌ ¼Ò¿äµÇ¸ç, ÃÖ´ë µ¿ÀÛ ÁÖÆļö¿¡¼ 1.4 msecÀÇ ½Ã°£ÀÌ ¼Ò¿äµÈ´Ù.
|
¿µ¹®³»¿ë (English Abstract) |
This paper describes a design of cryptographic processor supporting 233-bit elliptic curves over binary field defined by NIST. Scalar point multiplication that is core arithmetic in elliptic curve cryptography(ECC) was implemented by adopting modified Montgomery ladder algorithm, making it robust against simple power analysis attack. Point addition and point doubling operations on elliptic curve were implemented by finite field multiplication, squaring, and division operations over ɧɦ ÉåÉÖÉÖÉ×É× Éæ, which is based on affine coordinates. Finite field multiplier and divider were implemented by applying shift-and-add algorithm and extended Euclidean algorithm, respectively, resulting in reduced gate counts. The ECC processor was verified by FPGA implementation using Virtex5 device. The ECC processor synthesized using a 0.18 um CMOS cell library occupies 49,271 gate equivalents (GEs), and the estimated maximum clock frequency is 345 MHz. One scalar point multiplication takes 490,699 clock cycles, and the computation time is 1.4 msec at the maximum clock frequency.
|
Å°¿öµå(Keyword) |
Ÿ¿ø°î¼± ¾ÏÈ£
°ø°³Å° ¾ÏÈ£
¼öÁ¤Çü ¸ù°í¸Þ¸® ·¡´õ ¾Ë°í¸®µë
ECDH Å° ±³È¯ ÇÁ·ÎÅäÄÝ
ECC
public key cryptography
modified Montgomery ladder algorithm
ECDH key exchange protocol
|
ÆÄÀÏ÷ºÎ |
PDF ´Ù¿î·Îµå
|