2019³â Ãá°èÇмú´ëȸ
Current Result Document :
ÇѱÛÁ¦¸ñ(Korean Title) |
Cortex-M0 ±â¹ÝÀÇ º¸¾È SoC ÇÁ·ÎÅäŸÀÔ ¼³°è |
¿µ¹®Á¦¸ñ(English Title) |
A Design of Security SoC Prototype Based on Cortex-M0 |
ÀúÀÚ(Author) |
ÃÖÁعé
ÃÖÁØ¿µ
½Å°æ¿í
Jun-baek Choi
Jun-yeong Choe
Kyung-wook Shin
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¿ø¹®¼ö·Ïó(Citation) |
VOL 23 NO. 01 PP. 0251 ~ 0253 (2019. 05) |
Çѱ۳»¿ë (Korean Abstract) |
¸¶ÀÌÅ©·ÎÇÁ·Î¼¼¼¿¡ ºí·Ï¾ÏÈ£ Å©¸³Åä Äھ ÀÎÅÍÆäÀ̽ºÇÑ º¸¾È SoC (System-on-Chip) ÇÁ·ÎÅäŸÀÔ ±¸Çö¿¡ ´ëÇØ ±â¼úÇÑ´Ù. ¸¶ÀÌÅ©·ÎÇÁ·Î¼¼¼·Î Cortex-M0¸¦ »ç¿ëÇÏ¿´°í, ARIA¿Í AES¸¦ ´ÜÀÏ Çϵå¿þ¾î¿¡ ÅëÇÕÇÏ¿© ±¸ÇöÇÑ Å©¸³Åä Äھ IP·Î »ç¿ëµÇ¾ú´Ù. ÅëÇÕ ARIA-AES Å©¸³Åä ÄÚ¾î´Â ECB, CBC, CFB, CTR, OFBÀÇ 5°¡Áö ¿î¿µ¸ðµå¿Í 128-ºñÆ®, 256-ºñÆ®ÀÇ µÎ °¡Áö ¸¶½ºÅÍÅ° ±æÀ̸¦ Áö¿øÇÑ´Ù. ÅëÇÕ ARIA- AES Å©¸³Åä Äھ Cortex-M0ÀÇ AHB-light ¹ö½º ÇÁ·ÎÅäÄÝ¿¡ ¸Â°Ô µ¿ÀÛÇϵµ·Ï ÀÎÅÍÆäÀ̽º ÇÏ¿´À¸¸ç, º¸¾È SoC ÇÁ·ÎÅäŸÀÔÀº BFM ½Ã¹Ä·¹ÀÌ¼Ç °ËÁõ ÈÄ, FPGA µð¹ÙÀ̽º¿¡ ±¸ÇöÇÏ¿© Çϵå¿þ¾î-¼ÒÇÁÆ®¿þ¾î ÅëÇÕ °ËÁõÀ» ÇÏ¿´´Ù. |
¿µ¹®³»¿ë (English Abstract) |
This paper describes an implementation of a security SoC (System-on-Chip) prototype that interfaces a microprocessor with a block cipher crypto-core. The Cortex-M0 was used as a microprocessor, and a crypto-core implemented by integrating ARIA and AES into a single hardware was used as an intellectual property (IP). The integrated ARIA-AES crypto-core supports five modes of operation including ECB, CBC, CFB, CTR and OFB, and two master key sizes of 128-bit and 256-bit. The integrated ARIA-AES crypto-core was interfaced to work with the AHB-light bus protocol of Cortex-M0, and the crypto-core IP was expected to operate at clock frequencies up to 50 MHz. The security SoC prototype was verified by BFM simulation, and then hardware-software co-verification was carried out with FPGA implementation. |
Å°¿öµå(Keyword) |
º¸¾È SoC
¾ÏÈ£ ÇÁ·Î¼¼¼
ARIA
Cortex-M0
AHB ÇÁ·ÎÅäÄÝ
Key word Security SoC
cryptographic processor
ARIA
AES
Cortex-M0
AHB protocol
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